Skip to main content

About Me

My Resume: Prasad_Pandit_Resume.pdf 

Hello Everybody, I am Prasad Pandit an Electronics Engineer, a Freelancer. I completed my Engineering in 2012. I have a keen intrest in technology development and research. I am a beginner in VHDL, AVR and PCB designing. I am good at Single and Double layer PCB designing, Synthesizable VHDL coding, uC tinkering. is an initiative to help the Amatures and Beginners to get on development track. You can use this site to start with basic projects like blinking LED, Simple counter design etc. I have added some basic projects to start with you can check it in Project Archieves.

If you still want any basic projects like designing gates or if you want any tutorials on using Softwares like Quartus II, SOPC builder etc you can contact me. I will add it if I get sufficient response from your side.

VHDL is not that hard. Once you got it, You will be more valuable than Diamond. Never lose hope and don't ever try to give up. It takes time but yes it makes you even better.

"That man will win some other day, who loses with smile..."

Think VHDL in terms of Gates, Muxes, Flipflops, Clock, Register. Keep your C knowledge aside and you will find it easier than ever.
Enjoy Programming..

P.S. If you like our work, help us by paying through Paypal.

Mail me:

Youtube Channel: Pulsee250i

Popular posts from this blog

VHDL code for Clock Divider

This is a clock divider code, just set the max-count value as per your requirenment.

For ex. If I want 1Hz freq. set the max count to i/p freq value viz.
1sec = 1Hz
Then, to get time period of 1sec i.e. 1 Hz frequency set max-count to 240000 as shown below:

1sec  =  24000000  -- for i/p frequency of 24 MHz.

To get your desired frequency just calculate the maxcount with the formula given below:

max_count = 24000000 * (1/your required frequency)


1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48libraryIEEE; useIEEE.STD_LOGIC_1164.ALL; useIEEE.numeric_std.all; entityclk_divisPort ( Clk :instd_logic; rst :instd_logic; op :outstd_logic ); endclk_div; architecturebehavioralofclk_divisconstant max_count :natural:=24000000; -- I used 24MHz clockbeginprocess(Clk,rst) variable count :naturalrange0to max_count; beginif rst ='0'…

16x2 LCD Controller in VHDL

Hello Everybody. The LCD 16x2 code is ready. Just one bug which is still not recognized. You need to program code 2 times on board to see it work. I dont know why its behaving like that.

The text data is stored in a HEX file and is loaded onto the ROM of 32x8 byte size. It can be reconfigured easily.

I will be uploading code in short of time with some new features.

And after that be ready for a BMP decoder. Get ready with your pic to be seen on Monitor via FPGA.


I didnt made  changes to code, if you program fpga 2 times without turning it off the code works(It worked on my DE1 board)
I have uploaded project compiled for DE1 board, mail me your quiries, and if anyone finds bug in code.

Project zip Download:

0 to 9999 bcd counter on seven segment(VHDL code) Synthesizeble

--Note: while building Project do include sec_clk and seg7 files which i posted

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;

entity c09 is
port( rst,clk: in std_logic;
      op0,op1,op2,op3: out std_logic_vector(6 downto 0));
end c09;

architecture count of c09 is

component sec_clk
Port (
           clk             : in  std_logic;
           rst : in std_logic;
           op  : out std_logic
    end component;

component seg7
port(m: in integer range 0 to 15;
     num: out std_logic_vector(6 downto 0));
end component;

signal flag: std_logic;
signal a: integer range 0 to 10;
signal b: integer range 0 to 10;
signal c: integer range 0 to 10;
signal d: integer range 0 to 10;

c1: sec_clk port map(clk,rst,flag);

variable m0: integer range 0 to 10:=0;
variable m1: integer range 0 to 10:=0;
variable m2: integer range 0 to 10:=0;
variable m3: integer range 0 to 10:=0;


if rst='0' then