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Frequency counter in VHDL (Synthesizeble)

Its Done...!! The Frequency Counter or Measurer is ready. You can measure any I/P frequency from 3Hz to 95KHz i.e. (95,000 Hz for DE1 board Cyclone II FPGA).(This can be diffrent for difrent FPGAs according to their propogation delays and other time factors). Above this value the FPGA gets unstable and show at-random values.

There are 3 levels of Accuracy
  • Hz.
  • (displayed value) x 10 Hz.
  • (displayed value) x 100 Hz.
 I have put a reset button, which is Pushbutton when clicked initiate the frequency measurement process. It then holds the value for user to read.



Right now the free-reading i.e. without any initialization, feature is not added. I will add that soon.

Now, working with code :-

To make the code easy I have used my 0 to 9999 counter code and just made some small changes in it. The Clk freq used is 24MHz.

I created 4 files likewise,
  1. freqcount.vhd (Top-level Entity)
  2. sec_clk.vhd (To generate the time window, which is used for accuracy)
  3. sec_clktry.vhd (Here I added this file for demo so as to generate frequency in circuit itself)
  4. seg7.vhd (Integer to 7-seg converter)
  5. freqcount.sof (Quartus II file only for DE1 board)
  • Now, if you are measuring freq. which is below 9999 then follow the steps. 
  1. In sec_clk.vhd file, keep the max_count=48000000. 
  2. This will generate a 2 sec window (As i/p clock freq is 24MHz) in which the First second will be High i.e. '1' and Another second will be '0'.                                                  
  3. So the code I designed it as, when there is high i.e. '1' then for the i/p of freq to be measured for every high of that freq there is a count. 
  4. When the time window goes to Low level i.e. '0' the counting stops. The counted value is then displayed on Seven seg and is in Hz.
  5. If you have querries about how I generated the time window check my Clock Divider project here.
  6. To generate any freq to be measured follow the formula given below:
      The time window is of 1 sec i.e. as the i/p clock is of 24MHz i.e.(24000000Hz) then for generation of 1 sec it should count till 24000000. Now say you want to generate freq of 90 Hz then,

  replace the max_count value in sec_clktry by

max_count = 24000000/(freq you want at o/p)

max_count = 24000000/90

Then, max_count = 266666.66

Put max_count = 266666 in sec_clktry  for 90Hz freq.

Now, when you run the code then the sec_clktry freq will be given to freq counter and it then gives you at o/p.

If you want to measure any external freq. Then comment out the clki signal and sec_clktry component and portmap in architecture. And re instantiate the clki i/p in entity ports.

  • Now for measuring freq more than 9999 just change the value of max_count in sec_clk as follows,
  1. For freq x 10Hz accuracy, change max_count = 4800000 in sec_clk.vhd (This will generate 0.2 sec window).
  2. For freq x 100 Hz accuracy, change max_count = 480000 in sec_clk.vhd (This will generate 0.02 sec window).
I soon will upload video with full description. If you have any querries mail me at
  • prasadp4009@gmail.com
  • prasadp4009@vhdlcodes.com
Download links:
Enjoy Programming...!! Keep looking, more projects on way.

Video:






Comments

  1. Great design my family's looking for a new gadgets this one will be our topic.
    I’m from: Denon avr 1611 .

    ReplyDelete
  2. can you give me your pinout (.ufc) of the frequency counter?

    ReplyDelete
  3. will this design work for a variable input signal of 4- 20 hz with a variable duty cycle ?

    ReplyDelete

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