RTC on FPGA with manual set synthesizeble VHDL code.

Hey there, cheers to VHDL. I successfully added manual set feature in my previous RTC project. I am not going to copy whole code here. I am just adding the links of .vhd files. I also added the pre-compiled .sof file only for DE1 boards. There is a very small bug that while clicking the set button to enable min and hr set, it increments the hr or min value unintentionally. Else everything is working great.

(Input freq 24MHz., top-level entity DigiClock)



On DE1 board: Push button functions.
  • Key0: Reset
  • Key1: Hour set (Key3 kept pressed)
  • Key2: Minute set (Key3 kept pressed)
  • Key3: Set enable.
Download links:
Video : 
    Do test the codes. If you have any querries do comment or mail me at prasadp4009@gmail.com.

    Enjoy Programming..!!

    12 comments:

    1. Hey,could you have any idea for date,month and year expression. I'm working with this topic

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    2. @Binh: Its not that hard, just creat new components for date, month, year. Give the o/p of hour clock to date so after 24 hrs its value will be incremented. The o/p of date to month, and of mont to year.

      Create new process, which will tristate the o/p of clock on 7-seg and then display date, month and year one by one with small delay after pressing any push-button. And its done. If you want then I will add this feature to RTC code I posted. But try it by yourself first, that will only make you master.

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    3. Thanks for answer but not easy as you said. Because after 4 years, we meet a Feb with 29 days. I will try. But let me ask you 2 questions:
      1,For 7 segment expression module: output is std_logic_vector(6 downto 0).But for input, my teacher used to BCD(4 bit). Whether we can use input as directly an integer 0->9? Does it run in reality?
      2, I want to add an ADC module in my work. An easy way to do is use an external ADC(8 bit) and then fpga will receive ADC output and express result. I wonder if we can "code" internal ADC in fpga? Something like input is levels of voltage from sensor, then fpga can understand the difference between these levels( 10mV for each) to push out 8 bits out?

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    4. @Binh: 1. Yes, its possible and you can use Integer data type. But then you cant use that vhdl code as main entity. You had to decleare it as component in another entity and then send the integer data as component from your Main entity. Generally if unspecified then VHDL compiler will compile the Integer variable as 32-bit. But if you give it a range say 0 to 9 (for BCD) then it will only generate 4-bit register. You can check it from my modified 7-seg project file and also in this RTC code: http://jimmy-embedded-c-n-vhdl.blogspot.com/2010/08/bcd-to-seven-seg-decoder-modified-using.html

      2. Unfortunately there is no onchip ADC available on FPGA which we use. So you had to use the ADC IC.

      And the feb problem : Leap year can only get divided by 4 and others dont so design a code with this condition.

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    5. Why in your code, "process(x,rst)" you used falling_edge(x) instead of raising_edge(x)? Other sounds ok, well done!

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    6. @Binh: Very nice observation buddy. You just got corrected the error in code. Thats really a great help for me.

      When I was designing the code then I tried directly interfacing the Push Button to the process. As you know on DE1/DE2 board when button is not pressed then it has value '1' and when pressed '0'. For that I have made it falling_edge.

      But as it didn't worked, so I designed a clock for the incrementation and assigned the 'mi' o/p to 'x'.

      All these divided clocks works as '1' for half time and '0' for another. It means we should make it rising_edge else the first minute of clock after burning code will be only of 30 seconds. And rest all will be 60 seconds.

      Making it rising_edge will correct that error.
      I will upload the corrected code.
      Thanks again..!!

      And yes I have added Poll about projects quality, do vote. And keep posting your querries that will really help me, you and all our friends.

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    7. @Binh: I think if we make correction of falling_edge to rising_edge, it directly increments min to 1 at start due to the rising_edge. Seems I had to modify the code to correct these errors. You also try.

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    8. I think no problems for 1 minutes lead or lag (because of difference between seconds). Can you do buttons for date, month, year. I can't use buttons for them. Now I'm facing with coding for their expression. But it's still hard. For min, hr we can write sec_clk,min_clk for next module. I wrote hr_clk.But I think we can't write date_clk,month_clk. I intend to write like this:

      process(hr_clk)
      if year mode 4 =0
      if month=1,3,5...
      if day\=31 then...
      or we can use Mealy state machine. Can you help me because I am a new beginner in VHDL.

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    9. Could You post the .pof file for this??!!!

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    10. Thanks for your reference. I finished my projects well by myself!

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    11. @Jace: Uploaded pof file for project.. Enjoy..

      @Binh: Thats great buddy...!! Keep it up.. you can share your work on blog if you want to.. I will post the updated files..

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    12. i wanna ask,is it this program compatible with de2 board?...because my project using de2 board

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