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Display on VGA Monitor by FPGA(VHDL code Synthesizable, 640X480 resol, 60Hz)

This code is for displaying a simple ball bouncing on your monitor screen. As the monitor requires 60 Hz refresh rate i.e. to replace each pixel 60 times, it requires approx 40 ns. So to synchronize it with the FPGA processing speed, I used PLL with 50 MHz i/p clock dividing it to 25 MHz which scans each pixel in 40 ns.

The Video Synchronization file I created is VGAS which has 5 o/ps viz.
  • red_out
  • green_out
  • blue_out
  • horiz_sync_out
  • vert_sync_out
These are connected to the VGA controller which must have be present on your FPGA board (present on all DE series board of Altera, I dont know about Xilinx).
For the pins check the your board manual.

The VGAS.vhd file can be used as common file for all your FPGA projects(for dividing 50Hz clock as I have used PLL which is already present on DE1 board. So if you have DE1 board its well and good you can directly use the code with the syncclk.vhd included. If dont just a minor modification in i/p clock signal with 25MHz in VGAS.vhd and removing syncclk.vhd and its component in VGAS.vhd will work.)

The Ballm.vhd is used to create display on Monitor. For DE1 users you can diretly program the SOF file i hav provided in download links.

Post your replies and comments. For the projects or querries you have you can mail me on .

Be the follower, if you like my posts.

Enjoy programming.

Video link:

Download links for files:


  1. Thanks a lot for this.

  2. hye. do you have any tutorial on how to create font/letter on vga monitor using de1 board. I only know how to write in up1 board which use table.


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0 to 9999 bcd counter on seven segment(VHDL code) Synthesizeble

--Note: while building Project do include sec_clk and seg7 files which i posted

library ieee;
use ieee.std_logic_1164.all;
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entity c09 is
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           op  : out std_logic
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signal flag: std_logic;
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signal d: integer range 0 to 10;

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16x2 LCD Controller in VHDL

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I have uploaded project compiled for DE1 board, mail me your quiries, and if anyone finds bug in code.

Project zip Download: