Synthesizable RTC in VHDL

The code given is only for clock digit incrementation. For components in clock like min_clk and sec_clk, refer my previous codes.

VHDL code:

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity clk12 is
port(
      clk: in std_logic;
      rst: in std_logic;
      op: out std_logic;
      op0,op1,op2,op3: out std_logic_vector(6 downto 0)
      );
     
end clk12;

architecture clock of clk12 is


component sec_clk
Port (
           clk : in std_logic;
           op  : out std_logic
     );
    end component;

component min_clk
Port (
           clk : in std_logic;
           rst : in std_logic;
           op  : out std_logic
     );
    end component;
   
   
component seg7
port(m: in integer range 0 to 10;
     num: out std_logic_vector(6 downto 0));
end component;


signal flag: std_logic;
signal sflag: std_logic;

signal a: integer range 0 to 10;
signal b: integer range 0 to 6;
signal c: integer range 0 to 10;
signal d: integer range 0 to 3;


begin

c1: sec_clk port map(clk,sflag);
c2: min_clk port map(sflag,rst,flag);
op<=sflag;

process(flag,rst)

variable m0: integer range 0 to 10:=0;
variable m1: integer range 0 to 6:=0;
variable m2: integer range 0 to 10:=2;
variable m3: integer range 0 to 3:=1;

begin
     a<=m0;
     b<=m1;
     c<=m2;
     d<=m3;
     if rst='0' then
     m0:=0;
     m1:=0;
     m2:=2;
     m3:=1;    
     elsif rising_edge(flag) then
     if  m0/=9 then
         m0:= m0+1;
        elsif  m0=9 and  m1/=5  then
         m0:=0;
         m1:= m1+1;
        elsif  m0=9 and  m1=5 and  m2/=9 and  m3=0 then
         m0:=0;
         m1:=0;
         m2:= m2+1;
        elsif  m0=9 and  m1=5 and  m2=9 and  m3=0 then
         m0:=0;
         m1:=0;
         m2:=0;
         m3:=1;
        elsif  m3=1 and  m2/=2 and  m1=5 and  m0=9 then
         m2:= m2+1;
        elsif  m3=1 and  m2=2 and  m1=5 and  m0=9 then
         m0:=0;
         m1:=0;
         m2:=1;
         m3:=0;
        end if; 
        end if;   
   
    end process;
   
    z0: seg7 port map(a,op0);
    z1: seg7 port map(b,op1);
    z2: seg7 port map(c,op2);
    z3: seg7 port map(d,op3);

end clock;



Note: The clock cant be set manually. It starts from 12:00. I tried my best to add the manual set function but didnt succeed. But I assure that manual set will also be there in couple of time. Suggetions are most welcome.

Video link: http://www.youtube.com/watch?v=1dbTi2PMgcU

Quartus SOF file for DE1 board only: Digiclk(for DE1 board only).SOF

Check the new code with hr and min manual set: RTC with maual set

Enjoy Programming.

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