bcd to seven seg decoder (modified using integer data type) in vhdl(synthesizable)

This code is generally used as component:

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity seg7 is


port(m: in integer range 0 to 15; -- m is decleared as INTEGER
     num: out std_logic_vector(6 downto 0));
end seg7;

architecture s7 of seg7 is
begin
process(m)
begin
case m is
when 0 => num<="1000000";
when 1 => num<="1111001";
when 2 => num<="0100100";
when 3 => num<="0110000";
when 4 => num<="0011001";
when 5 => num<="0010010";
when 6 => num<="0000010";
when 7 => num<="1111000";
when 8 => num<="0000000";
when 9 => num<="0010000";
when 10 => num<="0001000";  -- hex(a)
when 11 => num<="0000011";  -- hex(b)
when 12 => num<="1000110";  -- hex(c)
when 13 => num<="0100001";  -- hex(d)
when 14 => num<="0000110";  -- hex(e)
when 15 => num<="0001110";  -- hex(f)
when others=> num<="1111111";
end case;
end process;
end s7;

Comments

Popular posts from this blog

Website is being updated with new UI!

VHDL code for Clock Divider

16x2 LCD Controller in VHDL